1. Field of the Invention
The present invention relates to a method and an apparatus for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of sub-patterns formed via different internal paths of the pattern generator.
Although applicable, in principle, to any desired integrated circuits, the present invention and the problems on which it is based are explained with regard to integrated DRAM circuits in silicon technology.
2. Description of the Related Art
When testing semiconductor devices at very high data rates(typically 800 Mbit/sec), very stringent requirements are imposed on the positioning accuracy of the signal edges of a corresponding test system. The required accuracy, e.g. for testing high performance DRAMs, is an error of less than 50 ps. High performance test systems in this accuracy range typically use a calibration method in which the signals generated by the tester are detected as near as possible to the interface to the semiconductor module, measured and corrected in terms of their temporal position.
In the accuracy range discussed, it is necessary to establish for the calibration of the test system a situation which approaches the real measurement situation as closely as possible. That concerns not only the implementation of the measurement setup for calibration but also the pulse train (“pattern”) driven by the driver of the test system. In this case, it is primarily important also to take account of the influence of different pulse trains, since (e.g. as a result of parasitic effects) the position of an edge can change depending on its history. Therefore, the test system should be calibrated with a pattern which covers all pulse trains that occur in the application.
A further boundary condition imposed on the calibration by many test systems is due to the fact that a signal at a pin is composed internally via different signal processing paths which, in principle, all have to be calibrated in separately. Thus, e.g. in specific test systems, rising and falling edges are generated by different hardware resources and have to be calibrated separately. Furthermore, the internal resources (here the timing generator below) of the test system often do not operate at the maximum signal frequency which can be generated by the system on the device, but rather at e.g. half or quarter the frequency, i.e. the timing generator not only generates two edges per cycle, but four or eight. The consequence of this is that directly successive edges are also generated via different signal paths and therefore have to be calibrated separately.
FIG. 4 Shows a Diagrammatic Illustration of a Known High—Speed Test System.
In FIG. 4, MG designates a pattern generator. The pattern generator MG contains a sequence generator SG, which generates a logical pulse shape (that is to say a sequence of 1/0 information items) LPF, and also a timing/format generator TFG, which converts the logical pulse shape LPF into a physical signal waveform PPF. The signal waveform PPF is output by the driver AT via a corresponding waveguide WL to the module to be tested DUT. During the calibration operation, the test tip PS takes up the signal from the module to be tested DUT and forwards it to the measuring device M.
Such high-speed test systems have hitherto been measured or calibrated with the aid of a suitable measuring device (e.g. oscilloscope, zero crossing detector). In this case, the test system drives only those edges whose generation path is currently intended to be calibrated, e.g. only rising edges of an individual signal path. As a result, it is possible in a simple manner to calibrate the individual signal paths in the test system.
This Method Has Two Essential Disadvantages:
Firstly, the calibration is necessarily carried out with a regular pattern, i.e. the generated signal is periodic with a fixed frequency and fixed duty ratio. Although that corresponds well to the situation with a clock signal for a device, for data and control signals pulse trains are applied irregularly to the module.
However, an irregular pattern generates a significantly broader frequency spectrum in the signal path than a regular pattern. As a result, shifts in the positioning of the signal edge can arise due to resonances, frequency-dependent propagation times and limitations in the rise times. The position of the signal edge becomes dependent on the history.
Secondly, the restriction to a single signal path often also means that the measurement frequency is reduced.
This occurs if e.g. the timing generator operates internally at a quarter of the output frequency and, therefore, in this case generates eight edges within its internal period. During the calibration, the timing generator is then permitted to generate the measured signals only for the edges which are actually intended to be calibrated. At the remaining times at which an edge is generated during testing, no edge is permitted to be generated during calibration, since otherwise a plurality of signal paths would determine and thus corrupt the measurement. This, too, can result in altered transmission properties, so that the calibration is not optimally adapted to the later application. Both points bring about a deterioration in the calibration accuracy during the module measurement.
An improved adaptation of the calibration to the conditions during the module test is afforded by the following method: for this purpose, a pseudorandom play is generated at the play frequency and this is measured using a digital sampling oscilloscope (DSO) in the cumulative measurement mode. This produces—by superposition of many different signal edges—a so-called data eye diagram. By evaluating this data eye diagram it is possible to determine and compensate for an incorrect calibration.
Although this method allows the conditions largely to be readjusted during the measurement, it is not possible, however, to take account of the individual signal paths of the test system separately from one another, since the data eye diagram is only produced by the superposition of all the edge types. Moreover, the use of an oscilloscope means that this method requires a very long time, so that it cannot be employed economically for the calibration of a highly parallel production test system.